CH0 Serializer
CH7 Serializer
TSEL[0]
TSEL[1]
From Decimator
Control Register 16h
Training Sequence 3:
Custom Pattern
Training Sequence 2:
101010101010
Training Sequence 1:
000000111111
CH0 Decimator Output
Serializer
Custom Pattern
Registers
10h and 11h
CH7 Decimator Output
DO0+
DO0-
DO7+
DO7-
ADC
Outputs
ADC12EU050
www.ti.com
SNAS444I –JANUARY 2008–REVISED APRIL 2013
Figure 20. LVDS Training Select operation
USING IOR MODE
As discussed in FUNCTIONAL DESCRIPTION, IOR mode provides instantaneous recovery from overload
conditions, with no ringing and correct data output as soon as the input returns in range.
Standard Use of IOR Mode
The recommended way to enable IOR mode is by setting bit 4 (IOR) of the Modulator Overload Control register
(04h). Setting this bit will enable IOR mode with the default settings for DGF in the Decimator Clipping Control
register (14h) and OL in the Modulator Overload Control register (04h). Setting the IOR mode bit to 0 will restore
DGF and OL to their default values, hence putting the chip back into ADC mode.
As can be seen in ELECTRICAL CHARACTERISTICS, using IOR mode gives a slight reduction in SNR
performance, and also a reduction of the full scale input range to 1.56Vpp differential.
Advanced Use of IOR Mode
The registers described above allow the user to customize IOR mode. In order to correctly set the DGF and OL
values, it is necessary to understand how the IOR mode functions. The implementation of IOR mode in the ADC
consists of analog and digital parts working in tandem.
The analog clipping circuitry, controlled by OL, is designed to protect the sigma delta modulator from large signal
inputs. Using an analog clamp, signals are soft-limited to the less than the 2.10Vpp full scale range of the
modulator. OL gives the value at which the circuit will begin to clamp.
The digital filter of the ADC12EU050 is where the full scale input range is selected and the hard limiting of the
signal takes place. DGF selects the gain of the digital filter, and hence the new full scale input range of the ADC.
In order to set a custom value for DGF, CGS, bit 7 of the Decimator Clipping Control register, must be set. The
DGF can then be set, based on the application requirements.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
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